positive justification
英 [ˈpɒzətɪv ˌdʒʌstɪfɪˈkeɪʃn]
美 [ˈpɑːzətɪv ˌdʒʌstɪfɪˈkeɪʃn]
网络 正调制
双语例句
- Design and realization of Positive justification based on FPGA
基于FPGA的正码速调整的设计与实现 - The Principle of the Bit Recovery of the Modelling Method for Positive/ Zero/ Negative Justification
模型法正/零/负码速调整的码速恢复原理 - Design on a Novel Wireless Positive/ Zero/ Negative Justification
一种新型无线信道正零负码速调整设计 - This method can be used not only to reduce the waiting time jitter caused by pointer adjust me nt but also to reduce that caused by traditional bit justification ( positive or positive/ zero/ negative justification).
这项技术不仅可以用来有效地减小指针调整候时抖动，而且还可以用来减小传统的比特调整（正调整，正／零／负调整）的候时抖动。 - First, this paper describes motivation for modelling positive/ zero/ negative justification and shortcomings of positive justification in application.
本文首先从正码速调整在系统应用中的问题和正/零/负码速调整存在的技术问题出发，说明模型法正/零/负码速调整的研究背景； - The digital multiplex equipment using the modelling method for positive/ zero/ negative justification which has reduced the jitter greatly is being applied in our country.
正/零/负码速调整数字复接设备采用输出抖动小的模型法正/零/负码速调整方法。这种复接设备国内正在推广应用。 - A New Method for Reducing the Waiting Jitter of Positive Justification
一种减小正码速调整等候抖动的新方法 - Plesiochronous/ Synchronous Multiplex Technique Using Positive/ Zero/ Negative Justification
正/零/负调整准同步/同步复接技术 - Based on two kinds of the frame structure of tributary mapping interface in synchronous transport module ( STM) recommended by CCITT, this paper analysises and calculates the stuff jitter with positive justification method and positve/ zero/ negative justification method respectively.
本文针对CCITT推荐的同步传送模块（STM）支路映射接口两类帧结构，分别用正码速调整与正/零/负码速调整方法分析计算了其相应的塞入抖动。 - Both positive/ Zero/ negative and positive justification are CCITT recommended justification method for international digital path.
正/零/负码速调整和正码速调整都是CCITT建议用于国家间数字通道的两种码速调整方式。 - The author's main tasks includes: 1.Implement the multiplexer of 4 El signals, the main circuit includes all digital phase-locked loop ( DPLL), HDB3 encode and decode, positive justification, the start of frame detect circuit, multiplex and demultiplex circuit.
实现4路E1信号到1路二次群信号的复分接，主要包括全数字锁相环、HDB3-NRZ编解码、正码速调整、帧头检测和复分接等。 - The modelling method for positive/ zero/ negative justification demands to design the unique circuit for the bit recovery at the receiver.
模型法正/零/负调整方法要求在码速恢复端采取特殊的码速恢复措施。 - The Principle and design of Positive Justification Rates in Coder of 34Mb/ s Digital Television
34Mb/s数字电视编码设备中正码速调整的原理和设计 - Finally, it introduces application of modelling positive/ zero/ negative justification in digital communication system.
最后简述模型法正/零/负码速调整在数字通信系统中的应用。 - Realizing positive justification and simple BER tester with a FPGA individually.
在FPGA上分别设计实现了正码速调整和简单误码率测试仪，并连接成功。 - In this paper we design and realize the circuit of 2M positive justification/ recovery, and we solve the problem of stuffing jitter by means of utilizing digital smoothing method.
设计实现了2M数据码速调整和恢复电路，并利用数据平滑技术解决了塞入抖动问题。 - Public sense used in public selection is in forms of public proof and false to make positive justification and negative defence for public selecting trueness.
公选中的公共理性主要使用公共证明和公共证伪的形式，为公选之真做正面论证和反面辩护。